1. Field of Invention
The present invention relates in general to the field of testing electronic circuit boards. More particularly, the present invention relates to a method of determining the moisture content in an electronic circuit board (e.g., a printed circuit board, a panel that includes one or more printed circuit boards, or a special printed circuit board test panel) using two test coupons and a comparison of capacitance measurements acquired from the two coupons, and an apparatus, design process and design structure therefor.
2. Background Art
The structure of the laminate within module sites of printed circuit boards (PCBs) may be damaged when the PCBs are subjected to soldering operations. The likelihood that this damage will occur increases with increasing soldering temperatures and, as a result, reliability risks for the PCBs increase as well. Plated through holes (PTHs) in the PCB, especially PTHs within module sites, are particularly vulnerable to this failure mechanism. Higher soldering temperatures are a consequence of compliance with the Restriction of Hazardous Substances Directive or RoHS. Under RoHS, eutectic tin/lead solder is replaced by lead-free solders (e.g., Sn—Ag—Cu solder) with higher melting temperatures.
A key factor in this failure mechanism is the rapid volatilization (during soldering) of water that is entrapped within the laminate during fabrication of the PCB. Specifically, water may be entrapped during aqueous processes that occur after the PCB is drilled and up to the early phases of plating of the drilled holes (to form PTHs). For a given PCB design and laminate material, the amount of water that is entrapped will vary (up to a point) with the details of some aspects of the fabrication process. Similarly, the effects of entrapped water upon the structural integrity of the laminate within a given PCB will vary with the PCB design, the laminate material, and some aspects of the fabrication process. It is important that a PCB fabricator take steps to minimize the amount of entrapped water within a given PCB. Unfortunately, direct measurements of water content (especially within module sites) are not practical.
Typically, direct measurement of the water content in a PCB, especially within module sites, is performed through a destructive testing technique. For example, the water content in a PCB may be determined by Karl Fischer (KF) titration, which requires the sample to be ground to a fine powder and then subjected to coulometric analysis.
It is also known to indirectly measure the water content in a PCB through capacitance. This concept is based upon the fact that the capacitance of a given laminate increases with increasing water content. Such a scheme is disclosed in U.S. Pat. No. 7,571,637 B2, issued Aug. 11, 2009 to Chen et al., entitled “DESIGN STRUCTURE FOR AN ON-CHIP REAL-TIME MOISTURE SENSOR FOR AND METHOD OF DETECTING MOISTURE INGRESS IN AN INTEGRATED CIRCUIT CHIP”, assigned to the same assignee as the present application. In the Chen et al. patent, an integrated circuit (IC) chip includes one or more moisture-sensing units and a moisture monitor. The moisture monitor can be configured to provide a real-time moisture detected-signal for signaling that moisture ingress into the integrated circuit chip has occurred by comparing the sense signals of the moisture-sensing units (e.g., the voltage on a voltage node Vc across a metal-insulator-metal (MIM) capacitor) to a threshold voltage. While the design structure disclosed in the Chen et al. patent may be effective for monitoring ingress of moisture into an integrated chip during the operational lifetime of the chip, the design structure does not address monitoring the ingress of moisture during fabrication of the integrated chip.
Another scheme for indirectly measuring moisture content in a PCB using capacitance is disclosed in an article by O'Toole et al., entitled “Pb-Free Reflow, PCB Degradation and Moisture Absorption”, published by DfR Solutions, College Park, Md., dated Jul. 16, 2009. In the O'Toole et al. article, two coupon designs were utilized to investigate the effect of Pb-free solder reflow on the degradation of PCBs. Each coupon contained three sections (i.e., Sections 1, 2 and 3) and a total of six test structures (i.e., Test Structures A, B, C, D, E and F) were incorporated into the design. The three sections of the PCB all consisted of the basic shield-over-shield copper plane design; however, they differed in their content of PTHs and non-functional pads. Section 1 of each coupon, which included Test Structure A, contained only copper planes without PTHs. Section 1 resulted in the largest shield-over-shield capacitance measurements and facilitated observation of clear trends for this data. Section 2 of each coupon, which included Test Structures B and C, contained copper planes, PTHs and nonfunctional pads on every layer. Section 2 allowed capacitance measurements to be made for both shield-over-shield and PTH-shield trends on the same coupon. Section 3 of each coupon, which included Test Structures D, E and F, contained copper planes, PTHs and nonfunctional pads on every other layer. In reflow simulation, Test Structures B and C showed much greater change in shield-over-shield capacitance measurements compared to Test Structure A.
The scheme disclosed in the O'Toole article has a number of disadvantages. Unfortunately, because Test Structure A contained only copper planes without PTHs, the clearances etched in the copper planes (sometimes referred to as a “swiss-cheese” pattern or “anti-pads”) for the PTHs were omitted along with the PTHs. The omission of the etched clearances from Test Structure A diminishes the usefulness of the comparison of the shield-over-shield capacitance measurements between Test Structure A and Test Structures B and C. In essence, this is an “apples and oranges” comparison because the area of copper planes without the etched clearances is larger than the area of the copper planes with the etched clearances—this is why the Section 1 resulted in the largest shield-over-shield capacitance measurements. Moreover, for each test structure disclosed in the O'Toole article, alternating planes of the PCB stack-up (i.e., the PCB stack-up consists of 26 layers of copper foil with dielectric between each layer) are tied to two different nodes (i.e., nodes A1 and A2 for Test Structure A, nodes B1 and B2 for Test Structure B, nodes C1 and C2 for Test Structure C). This arrangement does not facilitate capacitance measurements between individual planes of the PCB stack-up and, hence, it is not possible to measure water content in a particular area of the PCB stack-up. Finally, the scheme disclosed in the O'Toole article requires coupons taken from production panels to be exposed to reflow simulation—a costly and time-consuming step.
Therefore, a need exists for an enhanced mechanism for the non-destructive determination of the moisture content in an electronic circuit board (e.g., a PCB, a panel that includes one or more PCBs, or a special PCB test panel) using test coupons during fabrication.